VHDL サンプルコード | タナビボ~田中太郎の備忘録~

はじめに
サンプルコード

はじめに

VHDLを久しぶりに書こうと思ったら何もかも忘れていたので
見返すようにサンプルコード集を作成します。順次更新していきます。

サンプルコード

D-FF（非同期リセット）

library ieee;
use ieee.std_logic_1164.all;

entity sample is port(
    clk  : in std_logic;
    rst_n: in std_logic;
    din  : in std_logic;
    dout : out std_logic
);
end sample;
architecture rtl of sample is
begin
    process(clk, rst_n) begin
        if (rst_n = '0') then
            dout <= '0';
        elsif (clk = '1' and clk'event) then
            dout <= din;
        end if;
    end process;
end rtl;

D-FF（同期リセット）

library ieee;
use ieee.std_logic_1164.all;

entity sample is port(
    clk  : in std_logic;
    rst_n: in std_logic;
    din  : in std_logic;
    dout : out std_logic
);
end sample;
architecture rtl of sample is
begin
    process(clk) begin
        if (rst_n = '0') then
            dout <= '0';
        elsif (clk = '1' and clk'event) then
            dout <= din;
        end if;
    end process;
end rtl;

カウンタ

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sample is port(
    clk  : in std_logic;
    rst_n: in std_logic;
    din  : in std_logic_vector(2 downto 0);
    dout : out std_logic_vector(2 downto 0)
);
end sample;
architecture rtl of sample is
begin
    process(clk, rst_n) begin
        if (rst_n = '0') then
            dout <= (others => '0');
        elsif (clk = '1' and clk'event) then
            dout <= din + '1';
        end if;
    end process;
end rtl;

インスタンス（component宣言）

library ieee;
use ieee.std_logic_1164.all;

entity sample is port(
    clk  : in std_logic;
    rst_n: in std_logic;
    din  : in std_logic_vector(2 downto 0);
    dout : out std_logic_vector(2 downto 0)
);
end sample;
architecture rtl of sample is
    component sub is port(
        clk  : in std_logic;
        rst_n: in std_logic;
        din_sub  : in std_logic_vector(2 downto 0);
        dout_sub : out std_logic_vector(2 downto 0)
    );
    end component;
begin
    i_sub : sub port map(
        clk => clk,
        rst_n => rst_n,
        din_sub => din,
        dout_sub => dout
    );
end rtl;

library ieee;
use ieee.std_logic_1164.all;

entity sub is port(
    clk  : in std_logic;
    rst_n: in std_logic;
    din_sub  : in std_logic_vector(2 downto 0);
    dout_sub : out std_logic_vector(2 downto 0)
);
end sub;
architecture rtl of sub is
begin
    process(clk, rst_n) begin
        if (rst_n = '0') then
            dout_sub <= (others => '0');
        elsif (clk = '1' and clk'event) then
            dout_sub <= din_sub;
        end if;
    end process;
end rtl;

Package

library ieee;
use ieee.std_logic_1164.all;
entity dff is port(
    clk  : in std_logic;
    rst_b: in std_logic;
    din  : in std_logic;
    dout : out std_logic
);
end dff;
architecture rtl of dff is
begin
    process(clk, rst_b) begin
        if (rst_b = '0') then
            dout <= '0';
        elsif (clk = '1' and clk'event) then
            dout <= din;
        end if;
    end process;
end rtl;

library ieee;
use ieee.std_logic_1164.all;
package sample_pkg is
    component dff port(
        clk  : in std_logic;
        rst_b: in std_logic;
        din  : in std_logic;
        dout : out std_logic
    );
    end component;
end package;

library ieee;
use ieee.std_logic_1164.all;
entity sample is port(
    clk  : in std_logic;
    rst_b: in std_logic;
    din  : in std_logic;
    dout : out std_logic
);
end sample;
library work;
use work.sample_pkg.all;
architecture rtl of sample is
begin
    u1: dff port map(
        clk => clk,
        rst_b => rst_b,
        din => din,
        dout => dout
    );
end rtl;